hwtSimApiVerilator package

Module which generates, compiles and loads Python C-extension which is wrapper around Verilator simulation. Inputs are Verilog files and result is Python class of simulator which can be instantiated and simulated.

Submodules

hwtSimApiVerilator.fs_utils module

hwtSimApiVerilator.fs_utils.find_files(directory, pattern, recursive=True)

Find files by pattern in directory

hwtSimApiVerilator.fs_utils.working_directory(directory)

hwtSimApiVerilator.rtlSimulatorVerilator module

hwtSimApiVerilator.simulator_gen module

hwtSimApiVerilator.simulator_gen.generatePythonModuleWrapper(top_name: str, top_unique_name: str, build_dir: str, accessible_signals: List[Tuple[str, bool, bool, int]], extra_Extension_args: Dict[str, object] = {'extra_compile_args': ['-std=c++11'], 'include_dirs': ['/usr/local/share/verilator/include', '/home/docs/checkouts/readthedocs.org/user_builds/hwtsimapiverilator/checkouts/latest/hwtSimApiVerilator/c_files'], 'language': 'c++', 'libraries': ['boost_coroutine', 'boost_context', 'boost_system', 'common.cpython-38-x86_64-linux-gnu'], 'library_dirs': ['/home/docs/checkouts/readthedocs.org/user_builds/hwtsimapiverilator/checkouts/build/lib.linux-x86_64-3.8/hwtsimapi_verilator/verilator', '/home/docs/checkouts/readthedocs.org/user_builds/hwtsimapiverilator/checkouts/latest/hwtSimApiVerilator']})

Collect all c/c++ files into setuptools.Extension and build it

Parameters

  • top_name – name of top in simulation

  • top_unique_name – unique name used as name for simulator module

  • build_dir – tmp directory where simulation should be build

  • verilator_include_dir – include directory of Verilator

  • accessible_signals – List of tuples (signal_name, signal_phy_name, read_only, is_signed, type_width)

  • extra_Extension_args – additional values for setuptools.Extension constructor

Returns

file name of builded module (.so/.dll file)

hwtSimApiVerilator.simulator_gen.getSrcFiles(build_dir: str)
hwtSimApiVerilator.simulator_gen.loadPythonCExtensionFromFile(library_file_name: str, module_name: str)
hwtSimApiVerilator.simulator_gen.verilatorCompile(files: List[str], build_dir: str)

hwtSimApiVerilator.utils module

hwtSimApiVerilator.utils.collect_signals(top: hwt.synthesizer.unit.Unit)

collect list of all signals in the component format ( name: Tuple[str], phy_name:str, is_read_only: int, is_signed: int, size: Tuple[int])